In U.S. Pat. No. 5,059,821, Murabayashi et al. describe a driver circuit having a complementary pair of bipolar output transistors and a pair of CMOS inverter predriver circuits. Each predriver inverter is connected to one of the output transistors to control its ON/OFF operation. The predriver circuits have different switching thresholds which have been chosen to ensure that both output transistors are not ON at the same time during a transition, thereby reducing power consumption.
In U.S. Pat. No. 5,488,322, Kaplinsky describes a digital interface circuit having a pair of comparators controlling a pair of pull-up and pull-down output transistors, respectively. The comparators, preferably CMOS differential amplifiers, receive different reference voltages selected to allow the comparators to recognize the beginning of an input signal transition sooner. In particular, the comparator controlling the pull-up output transistor receives a 0.8 V reference, while the comparator controlling the pull-down output transistor receives a 2.0 V reference, where the circuit's nominal transition point is 1.5 V. Each comparator controls only one of the two output transistors. Further, only one comparator is active at a time, and the active comparator is disabled after the nominal transition point has been reached at the circuit output. Antidrift buffers maintain the output level until the next transition.
It has been discovered that comparators with the required speed dissipate a significant amount of DC power (typ., at least 1 mA) even when at rest. Moreover, when the input reference voltages are distant from the center point between the high and low voltage states, the comparators have asymmetric driving power. The circuit then tends to be very strong in pulling the output up, but slow in pulling the output down.
In U.S. Pat. No. 5,034,623, McAdams discloses a CMOS input buffer with hysteresis that includes a first n-channel pull-up transistor with its source connected to a voltage supply and its gate connected to a voltage reference generator to provide a first reference voltage on its drain, a first p-channel transistor with its source connected to the pull-up transistor to receive the first reference voltage and with its gate connected to an input of the buffer, second and third n-channel transistors connected in series between the first p-channel transistor's drain and a common potential, with their gates also connected to the input of the buffer, an inverter with its input connected to the drain of the first p-channel transistor and with its output forming an output of the buffer, and a fourth p-channel transistor with its gate connected to the buffer output, its drain connected to the series connection between the second and third transistors and its source connected to receive a second reference voltage. By appropriate sizing of the transistors, high and low level trip points of the circuit may be adjusted.
In IEEE Journal of Solid-State Circuits, vol. 31, no. 4, April 1996, pages 531-536, Iima et al. disclose a transient sensitive trigger circuit which uses a Schmitt-trigger to control activation of an upper or lower half of a second inverter portion connected in parallel with a first inverter portion. When the upper half is active during a high-to-low input signal transition, there are two p-channel pull-up paths versus only one n-channel pull-down path for the output, so that the logical threshold increases. During a low-to-high input signal transition, the lower half of the second inverter portion is active so that there are two n-channel pull-down paths versus only one p-channel pull-up path for the output, so that the logical threshold decreases. The circuit thus acts as an inverter with hysteresis. The Schmitt-trigger is responsive directly to the input signal of the circuit.
An object of the invention is to provide an improved digital interface circuit with increased speed, low current consumption during both rest and transitions, and symmetric pull-up and pull-down strength.